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digitally programmable sensor signal amplifier with emi filters ad8556 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2005C2007 analog devices, inc. all rights reserved. features emi filters at input pins specified from ?40c to +140c low offset voltage: 10 v maximum low input offset voltage drift: 65 nv/c maximum high cmrr: 94 db minimum digitally programmable gain and output offset voltage programmable output clamp voltage open and short wire fault detection low-pass filtering single-wire serial interface stable with any capacitive load soic_n and lfcsp_vq packages 4.5 v to 5.5 v operation applications automotive sensors pressure and position sensors precision current sensing strain gages functional block diagram 05448-053 vdd vss 1 2 3 +in ?in out a3 vdd vss 1 2 3 +in ?in out a4 v out vdd vss 1 2 3 +in ?in out a2 vdd vss 1 2 3 +in ?in out a1 vss 1 2 3 +in ?in out a5 r7 p4 r5 vdd digin vclamp r3 p2 p1 r1 r2 r4 r5 p3 vneg vpos dac logic emi filter emi filter emi filter rf emi filter filt/digout ad8556 vss emi filter figure 1.
ad8556 rev. a | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 general description ......................................................................... 3 specifications ..................................................................................... 4 electrical specifications ............................................................... 4 absolute maximum ratings ............................................................ 6 thermal resistance ...................................................................... 6 esd caution .................................................................................. 6 pin configurations and function descriptions ........................... 7 typical performance characteristics ..............................................8 theory of operation ...................................................................... 16 gain values ................................................................................. 17 open wire fault detection ....................................................... 18 shorted wire fault detection ................................................... 18 floating vpos, vneg, or vclamp fault detection ......... 18 device programming ................................................................. 18 emi/rfi performance ................................................................... 24 outline dimensions ....................................................................... 26 ordering guide .......................................................................... 26 revision history 12/07rev. 0 to rev. a changes to features.......................................................................... 1 changes to general description .................................................... 3 updated outline dimensions ....................................................... 26 changes to ordering guide .......................................................... 26 5/05revision 0: initial version
ad8556 rev. a | page 3 of 28 general description the ad8556 is a zero-drift, sensor signal amplifier with digitally programmable gain and output offset. designed to easily and accurately convert variable pressure sensor and strain bridge outputs to a well-defined output voltage range, the ad8556 accurately amplifies many other differential or single-ended sensor outputs. the ad8556 uses the analog devices, inc. patented low noise, auto-zero and digitrim? technologies to create an incredibly accurate and flexible signal processing solution in a very compact footprint. gain is digitally programmable in a wide range from 70 to 1280 through a serial data interface. gain adjustment can be fully simulated in-circuit and then permanently pro- grammed with reliable polyfuse technology. output offset voltage is also digitally programmable and is ratiometric to the supply voltage. the ad8556 also features internal emi filters on the vneg, vpos, filt and vclamp pins. in addition to extremely low input offset voltage, low input offset voltage drift, and very high dc and ac cmrr, the ad8556 also includes a pull-up current source at the input pins and a pull- down current source at the vclamp pin, which allows open wire and shorted wire fault detection. a low-pass filter function is implemented via a single low cost external capacitor. output clamping set via an external reference voltage allows the ad8556 to drive lower voltage adcs safely and accurately. when used in conjunction with an adc referenced to the same supply, the system accuracy becomes immune to normal supply voltage variations. output offset voltage can be adjusted with a resolution of better than 0.4% of the difference between vdd and vss. a lockout trim after gain and offset adjustment further ensures field reliability. the ad8556 is fully specified from ?40c to +140c. operating from single-supply voltages of 4.5 v to 5.5 v, the ad8556 is offered in the 8-lead soic_n and 4 mm 4 mm 16-lead lfcsp_vq.
ad8556 rev. a | page 4 of 28 specifications electrical specifications vdd = 5.0 v, vss = 0.0 v, v cm = 2.5 v, v o = 2.5 v, ?40c t a +140c, unless otherwise specified. table 1. parameter symbol conditions min typ max unit input stage input offset voltage v os ?40c t a +125c 2 10 v ?40c t a +140c 3 12 v input offset voltage drift t c v os 25 65 nv/c input bias current i b t a = 25c 38 49 54 na ?40c t a +125c 58 na ?40c t a +140c 60 na input offset current i os t a = 25c 0.2 2.5 na ?40c t a +125c 3.0 na ?40c t a +140c 4.0 na input voltage range 2.1 2.9 v common-mode rejection ratio cmrr v cm = 2.1 v to 2.9 v, a v = 70 80 92 db v cm = 2.1 v to 2.9 v, a v = 1280 94 112 db linearity v o = 0.2 v to 3.4 v 20 ppm v o = 0.2 v to 4.8 v 1000 ppm differential gain accuracy second stage gain = 17.5 to 100 0.35 1.6 % second stage gain = 140 to 200 0.5 2.5 % differential gain temperature coefficient second stage gain = 17.5 to 100 7 20 ppm/c second stage gain = 140 to 200 10 40 ppm/c rf 14 18 22 k rf temperature coefficient 600 ppm/c dac accuracy a v = 70, offset codes = 8 to 248 0.2 0.6 % ratiometricity a v = 70, offset codes = 8 to 248 50 ppm output offset a v = 70, offset codes = 8 to 248 5 35 mv temperature coefficient ?40c t a +125c 3.3 15 ppm fs/c ?40c t a +140c 25 ppm fs/c vclamp input bias current t a = 25c, vclamp = 5 v 200 na ?40c t a +125c, vclamp = 5 v 500 na ?40c t a +140c, vclamp = 5 v 550 na input voltage range 1.2 4.94 v output buffer stage buffer offset 3 7 mv short-circuit current i sc 5 10 ma output voltage, low v ol r l = 10 k to 5 v 20 mv output voltage, high v oh r l = 10 k to 0 v 4.94 v power supply supply current i sy ?40c t a +125c, v o = 2.5 v, vpos = vneg = 2.5 v, vdac code = 128 2.0 2.7 ma ?40c t a +140c, v o = 2.5 v, vpos = vneg = 2.5 v, vdac code = 128 2.78 ma power supply rejection ratio psrr a v = 70 109 125 db supply voltage required during programming 10 c < t prog < 40 c, supply capable of driving 250 ma 5.0 5.25 5.5 v
ad8556 rev. a | page 5 of 28 parameter symbol conditions min typ max unit dynamic performance gain bandwidth product gb p first gain stage, t a = 25c 2 mhz second gain stage, t a = 25c 8 mhz output buffer stage, t a = 25c 1.5 mhz output buffer slew rate sr a v = 70, r l = 10 k, c l = 100 pf, t a = 25c 1.2 v/s settling time t s to 0.1%, a v = 70, 4 v output step, t a = 25c 8 s noise performance input referred noise t a = 25c, f = 1 khz 32 nv/hz low frequency noise e n p-p f = 0.1 hz to 10 hz, t a = 25c 0.5 v p-p total harmonic distortion thd v in = 16.75 mv rms, f = 1 khz, a v = 100, t a = 25c ?100 db digital interface input current 2 a digin pulse width to load 0 tw 0 t a = 25c 0.05 10 s digin pulse width to load 1 tw 1 t a = 25c 50 s time between pulses at digin tw s t a = 25c 10 s digin low t a = 25c 1 v digin high t a = 25c 4 v digout logic 0 t a = 25c 1 v digout logic 1 t a = 25c 4 v
ad8556 rev. a | page 6 of 28 absolute maximum ratings table 2. parameter rating supply voltage 6 v input voltage vss ? 0.3 v to vdd + 0.3 v differential input voltage 1 5.0 v output short-circuit duration to vss or vdd indefinite storage temperature range ?65c to +150c operating temperature range ?40c to +150c junction temperature range ?65c to +150c lead temperature 300c 1 differential input voltage is limited to 5.0 v or the supply voltage, whichever is less. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 3. thermal resistance package type ja 1 jc unit 8-lead soic_n (r) 158 43 c/w 16-lead lfcsp_vq (cp) 44 31.5 c/w 1 ja is specified for the worst-case conditions, that is, ja is specified for device soldered in circuit board for lfcsp_vq package. esd caution
ad8556 rev. a | page 7 of 28 pin configurations and function descriptions 0 5448-002 vdd 1 filt/digout 2 digin 3 vneg 4 vss 8 vout 7 vclamp 6 vpos 5 ad8556 top view (not to scale) figure 2. 8-lead soic_n pin configuration 05448-003 12 11 10 9 nc vclamp nc vout 1 nc 2 3 5 nc vneg nc vpos 6 7 8 4 digin nc filt/digout 16 15 14 13 ad8556 top view pin 1 indicator avdd dvdd avss dvss nc = no connect figure 3.16-lead lfcsp_vq pin configuration table 4. pin function descriptions pin no. soic_n lfcsp_v mnemonic description 1 vdd positive supply voltage. 2 2 filt/digout unbuffered amplifier output in series with a resistor rf. adding a capacitor between filt and vdd or vss implements a low-pass filtering function. in read mode, this pin functions as a digital output. 3 4 digin digital input. 4 6 vneg negative amplifier input (inverting input). 5 8 vpos positive amplifier input (noninverting input). 6 10 vclamp set clamp voltage at output. 7 12 vout buffered amplifier output. buffered version of the signal at the filt/digout pin. in read mode, vout is a buffered digital output. 8 vss negative supply voltage. 13, 14 dvss, avss negative supply voltage. 15, 16 dvdd, avdd positive supply voltage. 1, 3, 5, 7, 9, 11 nc do not connect.
ad8556 rev. a | page 8 of 28 typical performance characteristics 05448-004 v os 5v (v) 10 ?10 ?5 0 5 hits 100 60 80 40 20 0 n: 363 mean: ?0.389938 sd: 1.65684 figure 4. input offset voltage distribution 05448-005 v cm (v) 3.5 1 . 52 . 02 . 53 . 0 v osi (v) 2.0 0.5 1.0 1.5 ?1.0 ?0.5 0 ?2.0 ?1.5 ?2.5 ?3.0 v sy = 5v t a = 25c figure 5. input offset voltage vs. common-mode voltage 05448-006 temperature (c) 150 ?50 ?25 0 25 50 75 100 125 input offset voltage (v) 10 8 6 4 2 0 ?2 ?4 ?6 ?8 ?10 v sy = 5v figure 6. input offset voltage vs. temperature 05448-007 t c v os (nv/c) more 0 10203040 number of amplifiers 25 15 20 10 5 0 v sy = 5v figure 7. t c v os at v sy = 5 v 05448-009 temperature (c) 150 ?50 ?25 0 25 50 75 100 125 buffer offset voltage (mv) 1.9 1.5 1.7 1.1 1.3 0.9 0.7 0.5 v out = 0.3v v out = 4.7v v sy = 5v figure 8. output buffer offset voltage? vs. temperature 05448-010 temperature (c) 150 ?50 ?25 0 25 50 75 100 125 input bias current (na) 100 10 1 v sy = 5v figure 9. input bias current at vpos, vneg vs. temperature
ad8556 rev. a | page 9 of 28 05448-011 v cm (v) 6 012345 i b (na) 100 10 1 i b ? i b + v sy = 5v t a = 25c figure 10. input bias current at vpos, vneg vs. common-mode voltage 05448-012 temperature (c) 150 ?50 ?25 0 25 50 75 100 125 input offset current (na) 0.8 0.6 0.5 0 ?0.2 0.2 0.3 ?0.3 ?0.5 ?0.6 ?0.8 v sy = 5v figure 11. input offset current vs. temperature 05448-013 digital input voltage (v) 6 012345 digital input current (a) 0 2.5 2.0 1.5 1.0 0.5 v sy = 5.5v figure 12. digital input current vs. digital input voltage (pin 4) 05448-014 vclamp voltage (v) 6 02 3 14 5 vclamp current (na) 10 1000 100 ?40c +25c +125c v sy = 5v figure 13. vclamp current over temperature at v s = 5 v vs. vclamp voltage 05448-015 supply voltage (v) 6 0123 5 4 supply current (ma) 3.0 2.5 2.0 1.5 0.5 1.0 0 t a = 25c figure 14. supply current (i sy ) vs. supply voltage 05448-016 temperature (c) 150 ?50 ?25 0 25 50 75 100 125 supply current (ma) 2.5 2.3 2.1 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5 v sy = 5v figure 15. supply current (i sy ) vs. temperature
ad8556 rev. a | page 10 of 28 05448-017 frequency (hz) 1m 100k 100 1k 10k cmrr (db) 40 80 120 0 v sy = 2.5v gain = 70 figure 16. cmrr vs. frequency 05448-018 frequency (hz) 1m 100 1k 10k 100k cmrr (db) 120 80 4 0 0 v sy = 2.5v gain = 1280 figure 17. cmrr vs. frequency 05448-019 temperature (c) 150 ?50 ?25 0 25 50 75 100 125 gain = 1280 gain = 800 gain = 400 gain = 100 gain = 70 cmrr (db) 145 135 125 115 105 95 85 75 v sy = 5v figure 18. cmrr vs. temperature at different gains 05448-020 frequency (khz) 10 5 0 voltage noise density (nv/ hz) 60 50 40 30 20 10 v sy = 2.5v gain = 70 figure 19. voltage noise density vs. frequency (0 hz to 10 khz) 05448-021 frequency (khz) 500 250 0 voltage noise density (nv/ hz) 30 25 20 15 10 5 v sy = 2.5v gain = 70 35 figure 20. voltage noise density vs. frequency (0 hz to 500 khz) 05448-022 time (1s/div) noise (v) 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 v sy = 2.5v gain = 1000 figure 21. low frequency input voltage noise (0.1 hz to 10 hz)
ad8556 rev. a | page 11 of 28 05448-023 time (1s/div) noise (v) 0.6 0.4 0.2 ?0.2 0 ?0.4 ?0.6 v sy = 2.5v gain = 70 figure 22. low frequency input voltage noise (0.1 hz to 10 hz) 05448-024 frequency (hz) 1k 100k 10k 1m gain = 1280 gain = 70 v sy = 2.5v c l = 40pf closed-loop gain (db) 60 40 20 0 figure 23. closed-loop gain vs. frequency measured at filt/digout pin 05448-025 frequency (hz) 1k 100k 10k 1m gain = 70 gain = 1280 v sy = 2.5v closed-loop gain (db) 60 40 20 0 figure 24. closed-loop gain vs. frequency measured at vout pin 05448-026 frequency (hz) 1k 100k 10k 1m 10m v sy = 2.5v gain (db) 4 8 0 ?4 ?8 figure 25. output buffer gain vs. frequency 05448-027 load capacitance (nf) 100 0.1 1 10 overshoot (%) 60 50 40 30 20 10 0 r s c l output buffer v sy = 2.5v r s = 0 ? r s = 10 ? r s = 20 ? r s = 50 ? r s = 100 ? figure 26. output buffer positive overshoot 05448-028 load capacitance (nf) 100.0 0.1 1.0 10.0 overshoot (%) 60 50 40 30 20 10 0 r s c l v sy = 2.5v r s = 0 ? r s = 10 ? r s = 20 ? r s = 50 ? r s = 100 ? figure 27. output buffer negative overshoot
ad8556 rev. a | page 12 of 28 05448-029 load current (ma) 10.0 0.01 0.10 1.00 vdd ? output voltage (v) 0.001 1.000 0.100 0.010 v sy = 2.5v sink source figure 28. output voltage to supply rail vs. load current 05448-030 temperature (c) 175 ?75 ?50 ?25 0 25 50 75 100 125 150 output short circuit (ma) ?15 15 12 6 3 0 9 ?3 ?6 ?9 ?12 sink 5v source 5v figure 29. output short circuit vs. temperature time (100s/div) voltage 2 4 0 3 2 1 0 05448-031 supply voltage v out figure 30. power-on response at 25c time (100s/div) voltage (1v/div) 5 6 4 3 2 1 0 05448-032 supply voltage v out figure 31. power-on response at 125c time (100s/div) voltage (1v/div) 5 6 4 3 2 1 0 05448-033 supply voltage v out figure 32. power-on response at ?40c 05448-034 temperature (c) 150 ?75 ?50 ?25 0 25 50 75 100 125 psrr (db) 100 150 135 130 125 145 140 120 115 110 105 v sy = 2.7v to 5.5v figure 33. psrr vs. temperature
ad8556 rev. a | page 13 of 28 05448-035 frequency (khz) 100 0.01 0.1 1 10 psrr (db) 140 120 100 80 60 40 20 0 v sy = 2.7v to 2.5v figure 34. psrr vs. frequency 05448-036 time (100s/div) vout (50mv/div) 2 t v sy = 2.5v gain = 70 c l = 0.1f f in = 10khz figure 35. small signal response at c l = 0.1 f and f in = 10 khz 05448-037 time (100s/div) vout (50mv/div) t 2 v sy = 2.5v gain = 70 c l = 100pf f in = 1khz figure 36. small signal response at c l = 100 pf and f in = 1 khz 05448-038 time (10s/div) vout (1v/div) 2 t v sy = 2.5v gain = 70 c l = 100pf figure 37. large signal response at c l = 100 pf 05448-039 time (10s/div) vout (1v/div) 2 t v sy = 2.5v gain = 70 c l = 0.05f figure 38. large signal response at c l = 0.05 f 05448-040 frequency (khz) 0.1 10 11 0 0 1 10 100 1k 1 m v sy = 2.5v a v = 70 figure 39. output impedance vs. frequency
ad8556 rev. a | page 14 of 28 05448-041 0 v 0 v v in v out ch1 50.0mv a ch1 ?21.0mv ch2 2.00v m 1.00s 2 1 figure 40. negative overload recovery (gain = 70) 05448-042 v in v out ch1 50.0mv a ch1 57.0mv ch2 2.00v m 1.00s 0v 2 0v 1 figure 41. positive overload recovery (gain = 70) v in ?2.5v 05448-043 ch1 10.0mv a ch1 ?9.40mv ch2 2.00v m 4.00s 0v 2 0v 1 figure 42. negative overload recovery (gain = 1280) 05448-044 v in v out ch1 10.0mv a ch1 8.40mv ch2 2.00v m 4.00s 0v 1 0v 2 figure 43. positive overload recovery (gain = 1280) a ch1 40.0mv 0.1f 0.1f ?v 2 9 4 ? 2 0 . 5 ? +v 4 1 6 7 8 5 10k? 1k? 10k ? out dut 4v pp gain = 70 offset = 128 v sy = 2.5v ch1 2.00mv ch2 2.00mv m 1.00s 2 1 05448-045 figure 44. settling time 0.1% 05448-046 0.1f 0.1f ?v 2 9 4 ? 2 0 . 5 ? +v 4 1 6 7 8 5 10k ? 1k ? 10k ? out dut 4v pp gain = 70 offset = 128 v sy = 2.5v 0 v 0 v 2 1 ch1 2.00mv ch2 2.00mv m 1.00s a ch1 40.0mv figure 45. settling time 0.01%
ad8556 rev. a | page 15 of 28 05448-047 frequency (hz) thd (%) 20 1k 2k 20010050 500 5k 10k 20k 0.10 1.00 0.20 0.50 0.02 0.05 0.01 v sy = 2.5v figure 46. thd vs. frequency
ad8556 rev. a | page 16 of 28 theory of operation a1, a2, r1, r2, r3, p1, and p2 form the first gain stage of the differential amplifier. a1 and a2 are auto-zeroed op amps that minimize input offset errors. p1 and p2 are digital potentiometers, guaranteed to be monotonic. programming p1 and p2 allows the first stage gain to be varied from 4.0 to 6.4 with 7-bit resolution (see table 5 and equation 1), giving a fine gain adjustment resolution of 0.37%. r1, r2, r3, p1, and p2 each have a similar temperature coefficient; therefore, the first stage gain temperature coefficient is lower than 100 ppm/c. ? ? ? ? ? ? ? ? ? ? ? ? 127 4 6.4 4 code gain1 (1) a3, r4, r5, r6, r7, p3, and p4 form the second gain stage of the differential amplifier. a3 is also an auto-zeroed op amp that minimizes input offset errors. p3 and p4 are digital potentiometers that allow the second stage gain to be varied from 17.5 to 200 in eight steps (see table 6 ). r4, r5, r6, r7, p3, and p4 each have a similar temperature coefficient; therefore, the second stage gain temperature coefficient is lower than 100 ppm/c. rf together with an external capacitor, connected between filt/digout and vss or vdd, form a low-pass filter. the filtered signal is buffered by a4 to give a low impedance output at vout. rf is nominally 18 k, allowing an 880 hz low-pass filter to be implemented by connecting a 10 nf external capacitor between filt/digout and vss or between filt/digout and vdd. if low-pass filtering is not needed, the filt/digout pin must be left floating. a5 implements a voltage buffer that provides the positive supply to a4, the amplifier output buffer. its function is to limit vout to a maximum value, useful for driving adcs operating on supply voltages lower than vdd. the input to a5, vclamp, has a very high input resistance. it should be connected to a known voltage and not left floating. however, the high input impedance allows the clamp voltage to be set using a high impedance source, such as a potential divider. if the maximum value of vout does not need to be limited, vclamp should be connected to vdd. a4 implements a rail-to-rail input and output unity-gain voltage buffer. the output stage of a4 is supplied from a buffered version of vclamp instead of vdd, allowing the positive swing to be limited. the maximum output current is limited between 5 ma to 10 ma. an 8-bit dac is used to generate a variable offset for the amplifier output. this dac is guaranteed to be monotonic. to preserve the ratiometric nature of the input signal, the dac references are driven from vss and vdd, and the dac output can swing from vss (code 0) to vdd (code 255). the 8-bit resolution is equivalent to 0.39% of the difference between vdd and vss, for example, 19.5 mv with a 5 v supply. the dac output voltage (vdac) is given approximately by () vssvssvdd code vdac +? ? ? ? ? ? ? + 256 0.5 (2) where the temperature coefficient of vdac is lower than 200 ppm/c. the amplifier output voltage (vout) is given by vout = gain ( vpos ? vneg ) + vdac (3) where gain is the product of the first and second stage gains. a3 a2 a4 a5 vdd vdd dac vss vss vdd vss vdd v dd vss vclamp vpos vss filt/ digout vout a1 vdd vss vneg r1 r3 r2 r5 r7 p4 r4 r6 rf p3 p2 p1 05448-001 figure 47. functional schematic
ad8556 rev. a | page 17 of 28 gain values table 5. first stage gain vs. first stage gain code first stage gain code first stage gain first stage gain code first stage gain first stage gain code first stage gain first stage gain code first stage gain 0 4.000 32 4.503 64 5.069 96 5.706 1 4.015 33 4.520 65 5.088 97 5.727 2 4.030 34 4.536 66 5.107 98 5.749 3 4.045 35 4.553 67 5.126 99 5.770 4 4.060 36 4.570 68 5.145 100 5.791 5 4.075 37 4.587 69 5.164 101 5.813 6 4.090 38 4.604 70 5.183 102 5.834 7 4.105 39 4.621 71 5.202 103 5.856 8 4.120 40 4.638 72 5.221 104 5.878 9 4.135 41 4.655 73 5.241 105 5.900 10 4.151 42 4.673 74 5.260 106 5.921 11 4.166 43 4.690 75 5.280 107 5.943 12 4.182 44 4.707 76 5.299 108 5.965 13 4.197 45 4.725 77 5.319 109 5.988 14 4.213 46 4.742 78 5.339 110 6.010 15 4.228 47 4.760 79 5.358 111 6.032 16 4.244 48 4.778 80 5.378 112 6.054 17 4.260 49 4.795 81 5.398 113 6.077 18 4.276 50 4.813 82 5.418 114 6.099 19 4.291 51 4.831 83 5.438 115 6.122 20 4.307 52 4.849 84 5.458 116 6.145 21 4.323 53 4.867 85 5.479 117 6.167 22 4.339 54 4.885 86 5.499 118 6.190 23 4.355 55 4.903 87 5.519 119 6.213 24 4.372 56 4.921 88 5.540 120 6.236 25 4.388 57 4.939 89 5.560 121 6.259 26 4.404 58 4.958 90 5.581 122 6.283 27 4.420 59 4.976 91 5.602 123 6.306 28 4.437 60 4.995 92 5.622 124 6.329 29 4.453 61 5.013 93 5.643 125 6.353 30 4.470 62 5.032 94 5.664 126 6.376 31 4.486 63 5.050 95 5.685 127 6.400 table 6. second stage gain and gain ranges vs. second stage gain code second stage gain code second stage gain minimum combined gain maximum combined gain 0 17.5 70 112 1 25 100 160 2 35 140 224 3 50 200 320 4 70 280 448 5 100 400 640 6 140 560 896 7 200 800 1280
ad8556 rev. a | page 18 of 28 open wire fault detection the inputs to a1 and a2, vneg and vpos, each have a com- parator to detect whether vneg or vpos exceeds a threshold voltage, nominally vdd ? 2.0 v. if (vneg > vdd ? 2.0 v) or (vpos > vdd ? 2.0 v), vout is clamped to vss. the output current limit circuit is disabled in this mode, but the maximum sink current is approximately 10 ma when vdd = 5 v. the inputs to a1 and a2, vneg and vpos, are also pulled up to vdd by currents ip1 and ip2. these are both nominally 49 na and matched to within 3 na. if the inputs to a1 or a2 are accidentally left floating, as with an open wire fault, ip1 and ip2 pull them to vdd, which would cause vout to swing to vss, allowing this fault to be detected. it is not possible to disable ip1 and ip2, nor the clamping of vout to vss, when vneg or vpos approaches vdd. shorted wire fault detection the ad8556 provides fault detection when vpos, vneg, or vclamp shorts to vdd and vss. figure 48 shows the voltage regions at vpos, vneg, and vclamp that trigger an error condition. when an error condition occurs, the vout pin is shorted to vss. table 7 lists the voltage levels shown in figure 48 . v pos v neg vss vinl vinh vdd vss vcll vdd v clamp vss vinl vinh vdd error error normal error normal error error normal 05448-048 figure 48. voltage regions at vpos, vneg, and vclamp that trigger a fault condition table 7. typical vinl, vinh, and vcll values (vdd = 5 v) voltage min (v) typ (v) max (v) vout condition vinh 2.95 3.0 3.05 short to vss fault detection vinl 1.95 2.0 2.05 short to vss fault detection vcll 1.05 1.1 1.15 short to vss fault detection floating vpos, vneg, or vclamp fault detection a floating fault condition at the vpos, vneg, or vclamp pins is detected by using a low current to pull a floating input into an error voltage range, defined in the shorted wire fault detection section. in this way, the vout pin is shorted to vss when a floating input is detected. tabl e 8 lists the currents used. table 8. floating fault detection at vpos, vneg, and vclamp mnemonic typical current goal of current vpos 49 na pull-up pull vpos above vinh vneg 49 na pull-up pull vneg above vinh vclamp 0.2 a pull-down pull vclamp below vcll device programming digital interface the digital interface allows the first stage gain, second stage gain, and output offset to be adjusted and allows desired values for these parameters to be permanently stored by selectively blowing polysilicon fuses. to minimize pin count and board space, a single-wire digital interface is used. the digital input pin, digin, has hysteresis to minimize the possibility of inadvertent triggering with slow signals. it also has a pull-down current sink to allow it to be left floating when programming is not being performed. the pull-down ensures inactive status of the digital input by forcing a dc low voltage on digin. a short pulse at digin from low to high and back to low again, such as between 50 ns and 10 s long, loads 0 into the shift register. a long pulse at digin, such as 50 s or longer, loads 1 into the shift register. the time between pulses should be at least 10 s. assuming vss = 0 v, voltages at digin between vss and 0.2 vdd are recognized as a low, and voltages at digin between 0.8 vdd and vdd are recognized as a high. the timing diagram example in figure 49 shows the waveform for entering code 010011 into the shift register.
ad8556 rev. a | page 19 of 28 code 010 01 1 waveform t w0 t ws t w0 t ws t ws t ws t w0 t ws t w1 t w1 t w1 05448-049 figure 49. timing diagram for code 010011 table 9. timing specifications timing parameter description specification t w0 pulse width for loading 0 into shift register between 50 ns and 10 s t w1 pulse width for loading 1 into shift register 50 s t ws width between pulses 10 s table 10. 38-bit serial word format field no. bits description 0 0 to 11 12-bit start of packet 1000 0000 0001 1 12 to 13 2-bit function 00: change sense current 01: simulate parameter value 10: program parameter value 11: read parameter value 2 14 to 15 2-bit parameter 00: second stage gain code 01: first stage gain code 10: output offset code 11: other functions 3 16 to 17 2-bit dummy 10 4 18 to 25 8-bit value parameter 00 (second stage gain code): 3 lsbs used parameter 01 (first stage gain code): 7 lsbs used parameter 10 (output offset code): all 8 bits used parameter 11 (other functions) bit 0 (lsb): master fuse bit 1: fuse for production test at analog devices bit 2: parity fuse 5 26 to 37 12-bit end of packet 0111 1111 1110 a 38-bit serial word is used, divided into 6 fields. assuming each bit can be loaded in 60 s, the 38-bit serial word transfers in 2.3 ms. table 10 summarizes the word format. field 0 and field 5 are the start-of-packet field and end-of- packet field, respectively. matching the start-of-packet field with 1000 0000 0001 and the end-of-packet field with 0111 1111 1110 ensures that the serial word is valid and enables decoding of the other fields. field 3 breaks up the data and ensures that no data combination can inadvertently trigger the start-of-packet and end-of-packet fields. field 0 should be written first and field 5 written last. within each field, the msb must be written first and the lsb written last. the shift register features power-on reset to minimize the risk of inadvertent programming power-on reset occurs when vdd is between 0.7 v and 2.2 v.
ad8556 rev. a | page 20 of 28 initial state initially, all the polysilicon fuses are intact. each parameter has the value 0 assigned (see table 1 1 ). table 11. initial state before programming second stage gain code = 0 second stage gain = 17.5 first stage gain code = 0 first stage gain = 4.0 output offset code = 0 output offset = vss master fuse = 0 master fuse not blown when power is applied to a device, parameter values are taken either from internal registers, if the master fuse is not blown, or from the polysilicon fuses, if the master fuse is blown. programmed values have no effect until the master fuse is blown. the internal registers feature power-on reset; therefore, the unprogrammed devices enter a known state after power-up. power-on reset occurs when vdd is between 0.7 v and 2.2 v. simulation mode the simulation mode allows any parameter to be temporarily changed. these changes are retained until the simulated value is reprogrammed, the power is removed, or the master fuse is blown. parameters are simulated by setting field 1 to 01, selecting the desired parameter in field 2, and the desired value for the parameter in field 4. note that a value of 11 for field 2 is ignored during the simulation mode. examples of temporary settings are as follows: ? setting the second stage gain code (parameter 00) to 011 and the second stage gain to 50 produces: 1000 0000 0001 01 00 10 0000 0011 0111 1111 1110. ? setting the first stage gain code (parameter 01) to 000 1011 and the first stage gain to 4.166 produces: 1000 0000 0001 01 01 10 0000 1011 0111 1111 1110. a first stage gain of 4.166 with a second stage gain of 50 gives a total gain of 208.3. this gain has a maximum tolerance of 2.5%. ? set the output offset code (parameter 10) to 0100 0000 and the output offset to 1.260 v when vdd = 5 v and vss = 0 v. this output offset has a maximum tolerance of 0.8%: 1000 0000 0001 01 10 10 0100 0000 0111 1111 1110. programming mode intact fuses give a bit value of 0. bits with a desired value of 1 need to have the associated fuse blown. because a relatively large current is needed to blow a fuse, only one fuse can be reliably blown at a time. therefore, a given parameter value may need several 38-bit words to allow reliable programming. a 5.25 v ( 0.25 v) supply is required when blowing fuses to minimize the on resistance of the internal mos switches that blow the fuse. the power supply voltage must not exceed the absolute maximum rating and must be able to deliver 250 ma of current. at least 10 f (tantalum type) of decoupling capacitance is needed across the power pins of the device during programming. the capacitance can be on the programming apparatus as long as it is within 2 inches of the device being programmed. an additional 0.1 f (ceramic type) in parallel with the 10 f is recommended within ? inch of the device being programmed. a minimum period of 1 ms should be allowed for each fuse to blow. there is no need to measure the supply current during programming. the best way to verify correct programming is to use the read mode to read back the programmed values. then, remeasure the gain and offset to verify these values. programmed fuses have no effect on the gain and output offset until the master fuse is blown. after blowing the master fuse, the gain and output offset are determined solely by the blown fuses, and the simulation mode is permanently deactivated. parameters are programmed by setting field 1 to 10, selecting the desired parameter in field 2, and selecting a single bit with the value 1 in field 4. as an example, suppose the user wants to permanently set the second stage gain to 50. parameter 00 needs to have the value 0000 0011 assigned. two bits have the value 1; therefore, two fuses need to be blown. because only one fuse can be blown at a time, this code can be used to blow one fuse: 1000 0000 0001 10 00 10 0000 0010 0111 1111 1110. the mos switch that blows the fuse closes when the complete packet is recognized and opens when the start-of-packet, dummy, or end-of-packet fields are no longer valid. after 1 ms, this second code is entered to blow the second fuse: 1000 0000 0001 10 00 10 0000 0001 0111 1111 1110. to permanently set the first stage gain to a nominal value of 4.151, parameter 01 needs to have the value 000 1011 assigned. three fuses need to be blown, and the following codes are used, with a 1 ms delay after each code: 1000 0000 0001 10 01 10 0000 1000 0111 1111 1110 1000 0000 0001 10 01 10 0000 0010 0111 1111 1110 1000 0000 0001 10 01 10 0000 0001 0111 1111 1110. to permanently set the output offset to a nominal value of 1.260 v when vdd = 5 v and vss = 0 v, parameter 10 needs to have the value 0100 0000 assigned. if one fuse needs to be blown, use the following code: 1000 0000 0001 10 10 10 0100 0000 0111 1111 1110. finally, to blow the master fuse to deactivate the simulation mode and prevent further programming, use code: 1000 0000 0001 10 11 10 0000 0001 0111 1111 1110. there are 20 programmable fuses. because each fuse requires 1 ms to blow, and each serial word can be loaded in 2.3 ms, the maximum time needed to program the fuses can be as low as 66 ms.
ad8556 rev. a | page 21 of 28 parity error detection a parity check is used to determine whether the programmed data of an ad8556 is valid, or whether data corruption has occurred in the nonvolatile memory. figure 50 shows the schematic implemented in the ad8556. va0 to va2 is the 3-bit control signal for the second stage gain, vb0 to vb6 is the 7-bit control signal for the first stage gain, and vc0 to vc7 is the 8-bit control signal for the output offset. pfuse is the signal from the parity fuse, and mfuse is the signal from the master fuse. the function of the 2-input and gate (cell and2) is to ignore the output of the parity circuit (par_sum signal) when the master fuse is not blown. parity_error is set to 0 when mfuse = 0. in the simulation mode, for example, parity check is disabled. after the master fuse is blown, that is, after the ad8556 is programmed, the output from the parity circuit (par_sum signal) is fed to parity_error. when parity_error is 0, the ad8556 behaves as a programmed amplifier. when parity_error is 1, a parity error is detected, and vout is connected to vss. the 18-bit data signal (va0 to va2, vb0 to vb6, and vc0 to vc7) is fed to an 18-input exclusive-or gate (cell eor18). the output of cell eor18 is the dat_sum signal. if there is an even number of 1s in the 18-bit word, dat_sum = 0; and if there is an odd number of 1s in the 18-bit word, dat_sum = 1. see table 12 for examples. after the second stage gain, first stage gain, and output offset are programmed, compute dat_sum and set the parity bit equal to dat_sum. if dat_sum is 0, the parity fuse should not be blown in order for the pfuse signal to be 0. if dat_sum is 1, the parity fuse should be blown to set the pfuse signal to 1. the code to blow the parity fuse is: 1000 0000 0001 10 11 10 0000 0100 01111111 1110. after setting the parity bit, the master fuse can be blown to prevent further programming, using the code: 1000 0000 0001 10 11 10 0000 0001 0111 1111 1110. signal par_sum is the output of the 2-input exclusive-or gate (cell eor2). after the master fuse is blown, set parity_error to par_sum. as previously mentioned, the ad8556 behaves as a programmed amplifier when parity_error = 0 (no parity error). on the other hand, vout is connected to vss when a parity error is detected, that is, when parity_error = 1. in01 in02 in03 in04 in05 in06 in07 in08 in09 in10 in11 in12 in13 in14 in15 in16 in17 in18 va0 va1 va2 vb0 vb1 vb2 vb3 vb4 vb5 vb6 vc0 vc1 vc2 vc3 vc4 vc5 vc6 vc7 eor18 out i0 dat_sum par_sum pfuse mfuse in1 in2 eor2 and2 in1 in2 parity_error i1 out i2 out 05448-050 figure 50. functional circuit of ad8556 parity check table 12. examples of dat_sum second stage gain code first stage gain code output offset code number of bits with 1 dat_sum 000 000 0000 0000 0000 0 0 000 000 0000 1000 0000 1 1 000 000 0000 1000 0001 2 0 000 000 0001 0000 0000 1 1 000 100 0001 0000 0000 2 0 001 000 0000 0000 0000 1 1 001 000 0001 1000 0000 3 1 111 111 1111 1111 1111 18 0
ad8556 rev. a | page 22 of 28 read mode the values stored by the polysilicon fuses can be sent to the filt/digout pin to verify correct programming. normally, the filt/digout pin is only connected to the second gain stage output via rf. during read mode, however, the filt/digout pin is also connected to the output of a shift register to allow the polysilicon fuse contents to be read. because vout is a buffered version of filt/digout, vout also outputs a digital signal during read mode. read mode is entered by setting field 1 to 11 and selecting the desired parameter in field 2. field 4 is ignored. the parameter value, stored in the polysilicon fuses, is loaded into an internal shift register, and the msb of the shift register is connected to the filt/digout pin. pulses at digin shift out the shift register contents to the filt/digout pin, allowing the 8?bit parameter value to be read after seven additional pulses; shifting occurs on the falling edge of digin. an eighth pulse at digin disconnects filt/digout from the shift register and terminates the read mode. if a parameter value is less than eight bits long, the msbs of the shift register are padded with 0s. for example, to read the second stage gain, this code is used: 1000 0000 0001 11 00 10 0000 0000 0111 1111 1110. because the second stage gain parameter value is only three bits long, the filt/digout pin has a value of 0 when this code is entered, and remains 0 during four additional pulses at digin. the fifth, sixth, and seventh pulses at digin return the 3-bit value at filt/digout, the seventh pulse returns the lsb. an eighth pulse at digin terminates the read mode. sense current a sense current is sent across each polysilicon fuse to determine whether it has been blown. when the voltage across the fuse is less than approximately 1.5 v, the fuse is considered not blown, and logic 0 is output from the otp cell. when the voltage across the fuse is greater than approximately 1.5 v, the fuse is considered blown, and logic 1 is output. when the ad8556 is manufactured, all fuses have a low resistance. when a sense current is sent through the fuse, a voltage less than 0.1 v is developed across the fuse, which is much lower than 1.5 v; therefore, logic 0 is output from the otp cell. when a fuse is electrically blown, it should have a very high resistance. when the sense current is applied to the blown fuse, the voltage across the fuse should be larger than 1.5 v; therefore, logic 1 is output from the otp cell. it is theoretically possible, though very unlikely, for a fuse to be incompletely blown during programming, assuming the required conditions are met. in this situation, the fuse could have a medium resistance, neither low nor high, and a voltage of approximately 1.5 v could be developed across the fuse. therefore, the otp cell could output logic 0 or logic 1, depending on temperature, supply voltage, and other variables. to detect this undesirable situation, the sense current can be lowered by a factor of 4 using a specific code. the voltage developed across the fuse would then change from 1.5 v to 0.38 v, and the output of the otp would be logic 0 instead of the expected logic 1 from a blown fuse. fuses blown correctly would still output logic 1. in this way, fuses blown incorrectly can be detected. another specific code would return the sense current to the normal (larger) value. the sense current cannot be permanently programmed to the low value. when the ad8556 is powered up, the sense current defaults to the high value. the low sense current code is: 1000 0000 0001 00 00 10 xxxx xxx1 0111 1111 1110. the normal (high) sense current code is: 1000 0000 0001 00 00 10 xxxx xxx0 0111 1111 1110. programming procedure for reliable fuse programming, it is imperative to follow the programming procedure requirements, especially the proper supply voltage during programming. 1. when programming the ad8556, the temperature of the device must be between 10c and 40c. 2. set vdd and vss to the desired values in the application. use simulation mode to test and determine the desired codes for the second stage gain, first stage gain, and output offset. the nominal values for these parameters are shown in table 5 , tabl e 6 , equation 2, and equation 3; use the codes corresponding to these values as a starting point. however, because actual parameter values for given codes vary from device to device, some fine tuning is necessary for the best possible accuracy. one way to choose these values is to set the output offset to an approximate value, such as code 128 for midsupply, to allow the required gain to be determined. then set the second stage gain so the minimum first stage gain (code 0) gives a lower gain than required, and the maximum first stage gain (code 127) gives a higher gain than required. after choosing the second stage gain, the first stage gain can be chosen to fine tune the total gain. finally, the output offset can be adjusted to give the desired value. after determining the desired codes for second stage gain, first stage gain, and output offset, the device is ready for permanent programming.
ad8556 rev. a | page 23 of 28 important: once a programming attempt is made for any fuse, there should be no further attempt to blow that fuse. if a fuse does not program to the expected state, discard the unit. the expected incidence rate of attempted but unblown fuses is very small when following the proper programming procedure and conditions. 3. set vss to 0 v and vdd to 5.25 v ( 0.25 v). power supplies should be capable of supplying 250 ma at the required voltage and properly bypassed as described in the programming mode section. use program mode to permanently enter the desired codes for the first stage gain, second stage gain, and output offset. blow the parity bit fuse if necessary (see parity error detection section). blow the master fuse to allow the ad8556 to read data from the fuses and to prevent further programming. 4. set vdd and vss to the desired values in the application. use read mode with low sense current followed by high sense current to verify programmed codes. 5. measure gain and offset to verify correct functionality. determining optimal gain and offset codes first, determine the desired gain: 1. determine the desired gain, g a (using the measurements obtained from the simulation). 2. use tabl e 6 to determine g 2 , the second stage gain, such that (4.00 1.04) < (g a /g 2 ) < (6.4/1.04). this ensures the first and last codes for the first stage gain are not used, thereby allowing enough first stage gain codes within each second stage gain range to adjust for the 3% accuracy. next, set the second stage gain: 1. use the simulation mode to set the second stage gain to g 2 . 2. set the output offset to allow the ad8556 gain to be measured, for example, use code 128 to set it to midsupply. 3. use tabl e 5 or equation 1 to set the first stage gain code c g1 , so the first stage gain is nominally g a /g 2 . 4. measure the resulting gain, g b . g b b b should be within 3% of g a . 5. calculate the first stage gain error (in relative terms) e g1 = g b /g b a ? 1. 6. calculate the error (in the number of the first stage gain codes) c eg1 = e g1 /0.00370. 7. set the first stage gain code to c g1 ? c eg1 . 8. measure the gain, g c . g c should be closer to g a than to g b . b 9. calculate the error (in relative terms) e g2 = g c /g a ? 1. 10. calculate the error (in the number of the first stage gain codes) c eg2 = e g2 /0.00370. 11. set the first stage gain code to c g1 ? c eg1 ? c eg2 . the resulting gain should be within one code of g a . finally, determine the desired output offset: 1. determine the desired output offset o a (using the measurements obtained from the simulation). 2. use equation 2 to set the output offset code c o1 such that the output offset is nominally o a . 3. measure the output offset, o b . o b b b should be within 3% of o a . 4. calculate the error (in relative terms) e o1 = o b /o b a ? 1. 5. calculate the error (in the number of the output offset codes) c eo1 = e o1 /0.00392. 6. set the output offset code to c o1 ? c eo1 . 7. measure the output offset, o c . o c should be closer to o a than to o b . b 8. calculate the error (in relative terms) e o2 = o c /o a ? 1. 9. calculate the error (in the number of the output offset codes) c eo2 = e o2 /0.00392. 10. set the output offset code to c o1 ? c eo1 ? c eo2 . the resulting offset should be within one code of o a .
ad8556 rev. a | page 24 of 28 emi/rfi performance real-world applications must work with ever increasing radio/magnetic frequency interference (rfi and emi). in situations where signal strength is low and transmission lines are long, instrumentation amplifiers, such as the ad8556, are needed to extract weak, small differential signals riding on common-mode noise and interference. additionally, wires and pcb traces act as antennas and pick up high frequency emi signals. the longer the wire, the larger the voltage it picks up. the amount of voltages picked up is dependent on the impedances at the wires, as well as the emi frequency. these high frequency voltages are then passed into the in-amp through its pins. all instrumentation amplifiers can rectify high frequency out-of- band signals. unfortunately, the emi/rfi rectification occurs because amplifiers do not have any significant common-mode rejection above 100 khz. once these high frequency signals are rectified, they appear as dc offset errors at the output. the ad8556 features internal emi filters on the vneg, vpos, filt, and vclamp pins. these built-in filters on the pins limit the interference bandwidth and provide good rfi suppression without reducing performance within the pass-band of the instrumentation amplifier. a functional diagram of the ad8556 along with its emi/rfi filters is shown in figure 51 . the ad8556 has built-in filters on its inputs, vclamp, and filter pins. the first-order, low-pass filters inside the ad8556 are useful to reject high frequency emi signals picked up by wires and pcb traces outside the ad8556. the most sensitive pin of any amplifier to rfi/emi signal is the noninverting pin. signals present at this pin appear as common-mode signals and create problems. the filters built at the input of the ad8556 have two different bandwidths: common mode and differential mode. the common- mode bandwidth defines what a common-mode rf signal sees between the two inputs tied together and ground. the emi filters placed on the input pins of the ad8556 reject emi/rfi suppressions that appear as common-mode signals. 05448-053 vdd vss 1 2 3 +in ?in out a3 vdd vss 1 2 3 +in ?in out a4 v out vdd vss 1 2 3 +in ?in out a2 vdd vss 1 2 3 +in ?in out a1 vss 1 2 3 +in ?in out a5 r7 p4 r5 vdd digin vclamp r3 p2 p1 r1 r2 r4 r5 p3 vneg vpos dac logic emi filter emi filter emi filter rf emi filter filt/digout ad8556 vss emi filter figure 51. block diagram showing emi/rfi built-in filters
ad8556 rev. a | page 25 of 28 to show the benefits that the ad8556 brings to new applications where emi/rfi signals are present, a part was programmed with a gain of 70 and a dc offset of 2.5 v to produce a vout of 0 v. a test circuit like that shown in figure 52 was used. figure 52 simulates the presence of a noisy common-mode signal, and figure 53 shows the response dc values at vout. ad8556 vcc vee filter data ?in +in vclamp vout +2.5 v ? 2.5 v u3 variable v3 1 2 3 45 6 7 8 +2.5v vout 05448-051 + ? figure 52. test circuit to show ad8556 performance exposed to common-mo de rfi/emi signals 05448-054 ?20 0 20 40 60 80 100 0 200 400 600 800 1000 1200 frequency (mhz) devi a tion from dc output (mv) non-enhanced for emi ad8556 (enhanced part for emi) figure 53. dc offset values at vout caused by frequency seep of input the differential bandwidth defines the frequency response of the filters with a differential signal applied between the two inputs, vpos (that is, +in ) and vneg (that is, Cin). figure 54 shows the circuit used to test for ad8556 emi/rfi susceptibility. the part is programmed as previously stated during the common-mode testing. ad8556 vcc vee filter data ?in +in vclamp vout +2.5 v ? 2.5 v u2 200mv p-p v2 1 2 3 45 6 7 8 +2.5v vout 0 5448-052 + ? figure 54. test circuit to show ad8556 performance exposed to differential mode rfi/emi signals the response of ad8556 to emi/rfi differential signals is shown in figure 55 . 05448-055 ?1400 ?1200 ?1000 ?800 ?600 ?400 ?200 0 200 400 600 0 200 400 600 800 1000 1200 frequency (mhz) dc offset (mv) ad8556 non-enhanced part figure 55. response of ad8556 to emi/rfi differential signals to make a board robust against emi, the leads at vpos and vneg should be as similar as possible. in this way, any emi received by the vpos and vneg pins will be similar (that is, a common-mode input), and rejected by the ad8556. furthermore, additional filtering at the vpos and vneg pins should give a better reduction of unwanted behavior compared with filtering at the other pins.
ad8556 rev. a | page 26 of 28 outline dimensions 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2440) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-012-aa figure 56. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters and (inches) 16 5 13 8 9 12 1 4 1.95 bsc pin 1 indicator top view 4.00 bsc sq 3.75 bsc sq coplanarity 0.08 exposed pad (bottom view) compliant to jedec standards mo-220-vggc 12 max 1.00 0.85 0.80 seating plane 0.35 0.30 0.25 0.80 max 0.65 typ 0.05 max 0.02 nom 0.20 ref 0.65 bsc 0.60 max 0.60 max pin 1 indicator 0.50 0.40 0.30 0.25 min 2.50 2.35 sq 2.20 010606-0 figure 57. 16-lead lead frame chip scale package [lfcsp_vq] 4 mm 4 mm body, very thin quad (cp-16-10) dimensions shown in millimeters ordering guide model temperature range package description package option AD8556ARZ 1 ?40c to +140c 8-lead soic_n r-8 AD8556ARZ-reel 1 ?40c to +140c 8-lead soic_n r-8 AD8556ARZ-reel7 1 ?40c to +140c 8-lead soic_n r-8 ad8556acpz-r2 1 ?40c to +140c 16-lead lfcsp_vq cp-16-10 ad8556acpz-reel 1 ?40c to +140c 16-lead lfcsp_vq cp-16-10 ad8556acpz-reel7 1 ?40c to +140c 16-lead lfcsp_vq cp-16-10 1 z = rohs compliant part.
ad8556 rev. a | page 27 of 28 notes
ad8556 rev. a | page 28 of 28 notes ?2005C2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05448-0-12/07(a)

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